The present invention relates to a method of manufacturing a semiconductor integrated circuit device and to semiconductor integrated circuit device technology; and, more specifically, the invention relates to a technology suitably applicable to the manufacture of semiconductor integrated circuit devices having a structure in which n-channel MIS (metal insulator semiconductor) transistors and p-channel MIS transistors are provided on the same semiconductor substrate.
An effective way to improve the level of integration and the drive capability of the MIS transistors is miniaturization, which in recent years has progressed rapidly.
With the advancement of miniaturization, however, various problems have surfaced. Because the supply voltage remains constant (i.e. the supply voltage is not decreased) while the MIS transistors are manufactured in increasingly fine patterns, the field intensity in the devices increases, which in turn has adverse effects, such as a short channel effect, on the device characteristics.
The short channel effect is an undesired phenomenon in which, as the channel length decreases, the area affected by a drain voltage increases to cover an area immediately below a gate electrode, pulling down the potential of the semiconductor substrate surface, and resulting in variations (fall) of threshold voltage and reduction in the actual channel length.
When this short channel effect becomes more significant, the drain current can no longer be controlled by the gate voltage-a so-called punch-through phenomenon that will cause an increased leakage current between source and drain. The punch-through thus causes degradation of, for example, the memory retention capability in the transfer gate of a DRAM (dynamic random access memory).
Technologies to avoid these problems have been proposed which, for example, provide at the end portions of the source and the drain of a MIS transistor, on the channel side, a semiconductor region of a high impurity concentration of the same conduction type as the impurity of the channel. Such a punch-through suppression technology is disclosed, for example, in Japanese Patent Laid-Open No. 136404/1993.
For CMOS transistors comprising an n-channel MISFET (hereinafter referred to as nMOS) and a p-channel MISFET (pMOS), a CMOS manufacturing method is disclosed in Japanese Patent Laid-Open No. 111461/1996, which provides a so-called pocket ion-implanted region to suppress the punch-through phenomenon.
This publication discloses the following method of fabrication. After NMOS and pMOS gate electrodes are formed, a first mask is formed that exposes the nMOS formation region and covers the pMOS formation. Using this first mask, ion implantation is performed to form a low impurity concentration diffusion layer in the NMOS region, followed by another ion implantation of p-type impurity to cover the front end of the low impurity concentration diffusion layer. Next, a second mask is formed that exposes the pMOS formation region and covers the nMOS formation region. Using this second mask, an ion implantation is carried out to form a low impurity concentration diffusion layer in the pMOS region, followed by another ion implantation of n-type impurity to cover the front end of the low-impurity concentration diffusion layer.
Then, a sidewall spacer is formed on the sidewall of the gate electrode. Next, a third mask is formed that exposes the pMOS formation region and covers the pMOS formation region. Using this third mask, an ion is implanted to form a high impurity concentration diffusion layer in the nMOS region. Next, a fourth mask is formed that exposes the pMOS formation region and covers the nMOS formation region. Using this fourth mask, an ion implantation is performed to form a high impurity concentration diffusion layer in the pMOS region.
With the above fabrication method, a CMOS can be provided that has an LDD structure and a pocket ion-implanted region for prevention of punch-through.